1. Field of the Invention
The present invention relates generally to an electrically erasable nonvolatile memory, particularly an electrically erasable and programmable read-only-memory (EEPROM) or electrically alterable ROM (EAROM). More specifically, the invention relates to an EEPROM with a stacked-gate cell.
2. Description of the Background Art
In recent years, various electrically erasable nonvolatile memories have been developed. However, such electrically erasable nonvolatile memories are disadvantageous for lower integration in comparison with ultraviolent ray erasable and programmable ROM (UV-EPROM). It has been considered that UV-EPROM is advantageous because each cell can be formed by one transistor. It is also considered that it is unlikely to obtain an EEPROM cell having a smaller cell size than that of an UV-EPROM.
For such UV-EPROM, a need for one time PROM (OTP) which is fabricated on a plastic package has been growing in view of its practical use. In other words, the usual UV-EPROM which is fabricated on a ceramic serdip package with a crystal window is expensive because of the high cost for material of the package. On the other hand, in the practical use, an EPROM is programmed only one time similarly to that of an ordinary ROM.
Because OTP permits only one writing and does not permit data erasure in the cells, an inspection for writing data in each cell cannot be performed after fabricating the device. This encounters serious problem for maintaining satisfactory liability of the products. Namely in case of ordinary fuse type or junction type PROM, since inspection can be performed by reading out stored data immediately after writing data, it is unnecessary to perform after assembling the package. However, in case of EPROM, a charge in a floating gate is apt to leak when a defective cell exists. This causes a retention problem resulting in a loss of written data. For this reason, for an EPROM, it is essential to perform an inspection for finding a read/write error so as to remove the product on which the read/write error is found. However, in case of an OTP, because it is not possible to perform inspection after assembling, removal of the defective product is not possible.
Some manufacturers request the user to perform aging at a temperature in a range of 125.degree. C. to 150.degree. C. after writing a program and thereafter performing a read test for removal of the defectives. Such an aging test is sometimes performed by the manufacturer when they offer program-writing service for the user. Despite such attempt, the difficulty of inspection after assembling borders for expansion of share of an EPROM remains.
In order to solve such problems, ISSCC Digest, page 168 to page 169, 1985; ISSCC Digest, page 76 to page 77, 1987; IEDM Digest, page 616 to page 619, 1985; and IEEE Electron Device Letter Vol. EDL-7, No. 8, 1986, page 465 to 467 propose EEPROM having a memory cell size comparable with that of UV-EPROM.
For example, ISSCC Digest, page 76 to page 77, proposes an EEPROM which has an erase gate to which an electron is injected from a floating gate for performing erasure. Such architecture requires the additional erase gate. When technologies for fabricating the erase gate is applied to an UV-EPROM which enables the cell size of an UV-EPROM to be smaller than the present, an EEPROM cannot be comparable in integration. Furthermore, in the proposed architecture, a control gate is extended so as to place one end at an equal level to the floating gate in parallel to the floating gate above a channel. Such construction necessarily bulk thereof so as not to allow desired integration.
On the other hand, IEDM Digest, page 616 to 617 proposes electrical erasure technologies for a memory cell having the same structure as UV-EPROM. In the proposal, a high potential is applied to a source region to inject an electron in the source region. Because the cell has the same structure, integration becomes equal to the UV-EPROM. Such technology is advantageous in view of integration but encounters difficulty in assurance of erasure of data. Namely, the cells aligned on each word line have source regions connected to each other. Therefore, erasure of the cells on one word line is performed simultaneously by applying equal voltages, e.g. +1.5 V, in theory. However, due to delicate fluctuation in the electrical condition in the floating gate and the gate insulation layer, threshold levels at respective cells tends to be fluctuated. This causes variation of the threshold level at a respective cell by erasure operation. For instance, in some cells, an erasure may cause the threshold level to be set at a standard threshold level, e.g. +1.0 V. On the other hand, in some cells an over-erasure which may cause a substantially low threshold level, e.g. - 1.5 V can occur. Such cells having a negative threshold level may operates in a depletion mode. For this reason, practical implementation of this technology is hardly expected.
On the other hand, IEEE electron Device Letter Vol. EDL-7, No. 8, 1986, page 465 to page 467 discloses erasure technology for memory cells, each having an identical structure to UV-EPROM. In the proposed technology, an erasure pulse varies its level between 0 V to write level for writing data in the floating gate. This technology is established based on a discovery of the phenomena in that holes enter into floating gate in response to trailing edge of HIGH level pulse. This technology has poor reliability. Furthermore, in erasure, a substantial level of drain current which is comparable with that required for writing, e.g. several mA for each bit, is required. Therefore, only one to several words can be erased simultaneously. Because of unacceptably low erasure efficiency, this proposal is not adapted for practical implementation.